leakage power
英 [ˈliːkɪdʒ ˈpaʊə(r)]
美 [ˈliːkɪdʒ ˈpaʊər]
网络 漏电功耗; 漏电流; 泄漏功耗; 泄漏功率; 漏电功率
双语例句
- An On-Demand Mechanism for Data Cache Leakage Power Management
面向访问需求的数据缓存泄漏功耗管理方法 - The leakage power issue is challenging high-performance microprocessor design, especially as feature size shrinks.
随着工艺尺寸的缩小，漏流功耗逐渐成为制约微处理器设计的主要因素之一。 - A strategy for temperature-aware leakage power estimation of macro-module
一种模块级的温度感知漏电功耗估计策略 - The pump shaft power is generally water, power, friction loss of power and leakage power of these three parts combined.
泵的轴功率一般为水功率、摩擦功率和泄漏损失功率这三部分的总和。 - So, how to save leakage power becomes a very important issue.
所以，如何节省漏电功率变成很重要的议题。 - ACG can automatically turn on or turn off the IP clock to not only reduce dynamic power but also reduce leakage power with the power gating technique.
这种技术在不影响性能的前提下，可以根据IP核的应用状况自动开关时钟，不但可以降低动态功耗，还可以结合门控电源技术降低漏电功耗。 - By it, the input vectors that produce the minimum leakage power could be searched out when circuit worked in standby or idle mode.
通过该方法，能够找出电路处于待机或空闲模式时产生静态功耗最低的输入向量。 - Secondly, a leakage power estimation method based on GA ( genetic algorithm) was proposed for CMOS circuits according to the static power dissipation depend upon the state of circuits when they worked in standby or idle mode.
其次根据电路处于待机或空闲模式时，静态功耗的大小与电路所处的状态有关的特点，提出了基于遗传算法（GA）的CMOS电路泄漏功耗估计方法。 - Leakage Power Optimization in High Performance General-Purpose Microprocessor Design
更低的功耗；功耗小于6W；高性能通用处理器中的漏电功耗优化 - Study on leakage power estimation and reduction methodology of CMOS circuit
CMOS电路泄漏功耗估算与降低方法研究 - An effective way to reduce the leakage power is by means of multithreshold CMOS technique, which can restrain the leakage current by adding a MOS transistor to low threshold circuit.
多阈值CMOS技术是一种降低电路漏电流功耗的有效方法.它通过接入高阈值MOS管来抑制低阈值模块的漏电流。 - This novel cache architecture can turn off some unused ways and run in configuration with low power, otherwise it runs in normal configuration, so it can reduce the average leakage power.
该结构通过门控Gnd技术来动态地关闭或开启部分cache路，使得cache结构可以在低功耗配置和正常配置之间切换，从而达到降低静态功耗的目的。 - In addition, a DVS technology is used reducing the leakage power in the TLB's memory cells by 90%.
此外，通过引入DVS技术将TLB存储单元中的漏电功耗减少90%以上。 - The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without performance degradation.
对一款真实SoC中浮点IP核的改造实验表明，在不降低性能的前提下，可以平均降低62.2%的动态功耗，同时理论上平均降低70.9%的漏电功耗。 - Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.
特别是多阈值时钟竞争型触发器，不仅可以降低电路的漏电流功耗，还能降低电路的时钟网络的功耗。 - It is important to reduce leakage power to improve battery life in portable systems employing periodic self-test, to increase reliability of test and to reduce test-cost.
降低测试时的漏电流对于延长需要周期性自测试的便携式系统电池寿命、提高测试的可靠性和降低测试成本都至关重要。 - A Fast Algorithm for Leakage Power Reduction by Input Vector Control
应用输入向量控制技术降低漏电功耗的快速算法 - It is well-known that leakage power dissipation caused by leakage current in CMOS circuits during test periods has become a significant part of the total power dissipation.
众所周知，CMOS电路测试时由漏电流引起的漏电流功耗在测试功耗中处于重要地位。 - The pump performance would be affected by the two clearances in such a way that the clearance alters both volumetric leakage power loss and mechanical power loss ( dick friction loss of impeller).
口环间隙通过改变离心油泵的容积损失功率和机械损失功率（叶轮圆盘摩擦损失）影响离心油泵性能。 - Simulation results show that, this method can reduce the leakage power consumption of Cache by 69.2%, and make the overall performance of the processor reduced less than 2%.
经过模拟实验表明，采用该优化机制可以降低Cache漏电流功耗69.2%，而处理器整体性能损失平均不到2%。 - Specially, the leakage power will exceed dynamic power and becomes the most important factor for microprocessor design. Obvious leakage power will not only increase the microprocessors 'energy consumption and the manufacture cost, but also influences the microprocessors' stability and credibility.
其中，漏流功耗逐渐超越动态功耗成为微处理器功耗的决定因素，漏流功耗的显著增加不但导致能源消耗和制造成本增加，而且给微处理器工作的稳定性和可靠性带来严峻的挑战。 - Besides, the non-volatile memory has advantages such as low leakage power and high density.
另外，新型非易失性存储器由于其静态能耗低、密度大等特点，被考虑作为低功耗存储系统的实现。 - IVC technology is the main point of this thesis, and different algorithms for reducing leakage power reduction are analyzed. Finally, an algorithm based on genetic algorithm to solve the MLV of IVC technology is proposed for CMOS leakage power reduction.
IVC技术是本文重点研究的技术，为此，本文分析比较了多种应用IVC技术降低静态漏电功耗的算法。最后，本文在CMOS静态功耗优化中提出了一种改进的遗传算法用于求解IVC技术的MLV。 - At last, we can utilize P-type CMOS techniques to reduce the leakage power of the adiabatic circuits.
最后，本文还提出采用P型CMOS功控技术对绝热电路的漏功耗减小进行了初步探索与研究。 - The proposed circuit can adaptively adjust the power supply to its optimal value during the whole standby period, which results in considerable reduction of leakage power and effective compensation of process and temperature variations.
本文提出的自适应电源电压调整技术能够在很大程度上降低电路待机时的漏电功耗，有效弥补了工艺和温度变化对电路造成的影响，性能较好。 - The work and innovation are completed in the following: The existing problem of sparse channel model is analyzed. The parameter fast fading channels model is derived without aliasing and leakage power, and has more sparse and low computational complexity.
本人所完成的工作和创新点：分析了现有稀疏信道模型的问题，推导不会引起功率混叠与泄漏、稀疏性更强和计算复杂度低的基于参数化快衰落信道模型。 - Primary user receivers detections include the detection of the LO leakage power and the detection based on interference temperature.
主用户接收端检测包括本振泄漏功率检测和基于干扰温度的检测。 - With the development of integration magnitude, Along with the improvements in the technology, leakage power reduction of CMOS circuit became the top challenge in nanometer level.
随着工艺技术的不断进步和电路集成度的不断提高，CMOS电路的静态漏电功耗已经开始成为纳米级设计领域所面临的最严峻的挑战之一。 - When deep into sub-micro process, some new problems have been detected, such as exponential increase of leakage power that leads to a series of significant hot topics.
进入深亚微米工艺后，出现了很多新的功耗问题，例如漏电流的迅猛增长引起了一系列新问题的产生。